Zealogics IT Solutions
9th Floor, A1, Trans Asia Cyber Park Infopark Phase-II, Cochin
FPGA verification engineer
Understand design specs and develop verification plans for various design.
Test Bench development in system Verilog targeting complete functionality coverage.
Support of system Verilog assertion and coverage-driven methodology
Verify SoC using advanced verification methodologies -Emulation, FPGA Prototyping, ABV, Directed/ Constrained – Random verification.
Collaborate with digital design team to debug test cases and deliver functionally accurate designs.
Develop UVM based SV test benches
Define block, sub-system and SoC top level test plans.
Verification of IP and SOC logic using advanced verification methodologies – UVM, FPGA prototyping, emulation, etc.
Job Type: Full-time
Email - firstname.lastname@example.org
Address: Transasia Cyber Park, Suite 9A1 Infopark Phase II, Kochi, Kerala 682303, India